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CONTINUOUS ARRAY READ: By supplying an initial starting address for the main memory
array, the Continuous Array Read command can be utilized to sequentially read a continuous
stream of data from the device by simply providing a clock signal; no additional addressing
information or control signals need to be provided. The DataFlash incorporates an internal
address counter that will automatically increment on every clock cycle, allowing one continu-
ous read operation without the need of additional address sequences. To perform a
continuous read, an opcode of 68H or E8H must be clocked into the device followed by three
address bytes (which comprise the 24-bit page and byte address sequence) and a series of
don ’ t care bytes (four don ’ t care bytes if using the serial interface or 60 don ’ t care bytes if
using the parallel interface). The first 13 bits (PA12 - PA0) of the 24-bit (three byte) address
sequence specify which page of the main memory array to read, and the last 11 bits (BA10 -
BA0) of the 24-bit address sequence specify the starting byte address within the page. The
four or 60 don ’ t care bytes that follow the three address bytes are needed to initialize the read
operation. Following the don ’ t care bytes, additional clock pulses on the SCK/CLK pin will
result in data being output on either the SO (serial output) pin or the parallel output pins (I/O7-
I/O0).
The CS pin must remain low during the loading of the opcode, the address bytes, the don ’ t
care bytes, and the reading of data. When the end of a page in main memory is reached dur-
ing a Continuous Array Read, the device will continue reading at the beginning of the next
page with no delays incurred during the page boundary crossover (the crossover from the end
of one page to the beginning of the next page). When the last bit (or byte if using the parallel
interface mode) in the main memory array has been read, the device will continue reading
back at the beginning of the first page of memory. As with crossing over page boundaries, no
delays will be incurred when wrapping around from the end of the array to the beginning of the
array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the output
pins (SO or I/O7-I/O0). The maximum SCK/CLK frequency allowable for the Continuous Array
Read is defined by the f CAR specification. The Continuous Array Read bypasses both data
buffers and leaves the contents of the buffers unchanged.
BURST ARRAY READ WITH SYNCHRONOUS DELAY: The Burst Array Read with Synchro-
nous Delay functions very similarly to the Continuous Array Read operation but allows much
higher read throughputs by utilizing faster clock frequencies. It incorporates a synchronous
delay (through the use of don't care clock cycles) when crossing over page boundaries. To
perform a Burst Array Read with Synchronous Delay, an opcode of 69H or E9H must be
clocked into the device followed by three address bytes (which comprise the 24-bit page and
byte address sequence) and a series of don't care bytes (four don't care bytes if using the
serial interface or 60 don't care bytes if using the parallel interface). The first 13 bits (PA12-
PA0) of the 24-bit (three byte) address sequence specify which page of the main memory
array to read, and the last 11 bits (BA10-BA0) of the 24-bit address sequence specify the start-
ing byte address within the page. The don't care bytes that follow the three address bytes are
needed to initialize the read operation. Following the don't care bytes, additional clock pulses
on the SCK/CLK pin will result in data being output on either the SO pin or the I/O7-I/O0 pins.
4
AT45DB642
1638F – DFLSH – 09/02
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